Huawei Mate 60 Pro: what about the HiSilicon 9000s SoC?

The Kirin series is the flagship model for high-end smartphones.

In 2020, HiSilicon unveiled the Kirin 9000 to power the Huawei Mate 40 Series. This chip was manufactured using TSMC’s 5nm technology. In 2023, Huawei introduced the Mate 60 Pro smartphone, featuring HiSilicon’s newborn SoC, the Kirin 9000s, as the main processor.

The chip itself has the following dimensions: 14.5 x 14.3 x 0.4mm3, with a 207mm2 area and 0.35µm ball pitch. It includes the HiSilicon Kirin 9000s SoC die package and DRAM package … What’s inside?

Yole Group releases the technology, process, and cost analysis/report, ‘HiSilicon Kirin 9000s SoC in Huawei Mate 60 Pro’. This analysis provides significant insights into the technical choices made by HiSilicon and the company behind it, smartphone manufacturer, Huawei. This new report also delivers an insightful analysis of the manufacturing cost and selling price.

Based on a complete Huawei Mate 60 Pro teardown available in Yole Group’s Consumer Teardown Tracks, Phone module, the HiSilicon Kirin 9000s SoC report reveals multiple details surrounding the processor and the integration of the LPDDR5 DRAM package atop the SoC die package on the main board. Indeed, it gives numerous analyses ranging from the SoC die FEOL and back-end construction to the assembly. With this new report, Yole Group’s analysts aim to provide an understanding of the technical breakthroughs and related manufacturing processes offered by the Chinese company HiSilicon.

This new report highlights the top view and cross-section of the SoC using optical microscopy, CT-scan, SEM, and EDS to analyse the structure and materials. It also presents a complete analysis of SMIC’s N+2 FinFET using TEM.

This report also offers a detailed comparative analysis of the Kirin 9000 and Kirin 9000s, encompassing packaging to SoC die characteristics and furnishes a complete cost analysis.

Ying-Wu LiuTechnology and Cost Analyst, Computing and Software at Yole Group: “At Yole Group, we confirm that the chip fabrication differs from HiSilicon’s previous solution, the Kirin 9000. Indeed, we assumed the 9000s SoC die has been developed and manufactured using SMIC’s N+2 (7 nm) process, with 13 metal layers.”

For the DRAM package, two leading suppliers of LPDDR5 DRAM have been identified in Yole Group’s analysis: SK Hynix and Samsung. In this analysis, Yole Group has focused on the SoC with an SK Hynix memory package. The DRAM package (0.45mm) is stacked on the HiSilicon Kirin 9000s SoC die package (0.40mm).

The whole chip is assembled using PoP technology and then connected to the main board of the smartphone. PoP technology allows processor manufacturers to integrate DRAM packages from different suppliers.

The DRAM package connects to the SoC die package using DRAM package balls. The SoC die package is connected to the main PCB using SoC package balls. It consists of a top substrate with an embedded layer and a bottom substrate. The copper core solder balls in the embedded layer are used as an electric connection between the top and bottom substrates.

The SoC die is integrated into the embedded layer and flip-chipped onto the bottom substrate. According to Yole Group’s analysis, there are twelve metal layers in the main PCB.

There was a complete substitution of US devices and a significant reduction in Japan-sourced devices as well in 2024 with the Mate 60 Pro. Domestically sourced devices from mainland China now make up 50% of the design win count; more importantly, they comprise the most critical components of this premium segment phone.