Global Unichip Boosts Design Productivity with Cadence Encounter Timing System

By integrating Encounter Timing System into its traditional timing and noise signoff solution, GUC has established a robust environment for timing optimization during the placement and routing stage and final signoff verification. The analysis capabilities of the Encounter Timing System are integrated into the EDI System, giving GUC a single, consistent analysis view. This view enables signoff to drive implementation, which improves consistency and accelerates design closure through final timing signoff.

“Time to production is the key to the success of our company; most importantly, to the success of our customers,” said Chi-Chiang Hsieh, vice president of Global Unichip, “So, we are glad to see the turnaround time reduction in signoff iterations that Encounter Timing System brings to our Silicon Realization flow.”

EDI System delivers a comprehensive solution for advanced design closure. Sharing a common infrastructure with EDI System, Encounter Timing System enables faster engineering change orders (ECOs) between the implementation and signoff environments, resulting in better signoff verification and a dramatic reduction in late-stage design iterations. In addition, the intuitive graphical debug capabilities of Encounter Timing System help designers to accelerate root-cause and bottleneck analysis, potentially shaving weeks off tapeout schedules.

“We are delighted that GUC has achieved this important productivity enhancement with the Cadence Encounter Timing System,” said David Desharnais, product management group director at Cadence. “Addressing the productivity gap for customers is a key element of our EDA360 strategy. GUC’s continued adoption of Cadence solutions to improve design cycle efficiency is another example of our commitment to provide our customers with a Silicon Realization environment that addresses today’s most complex design challenges and improves their competitive edge in the market.”