Forte Design Systems Joins TSMC Reference Flow 11.0 with Cynthesizer

“TSMC and Forte have been working together to meet the unique challenges associated with ESL design,” remarks Tom Quan, TSMC’s deputy director of Design Service Marketing. “Forte provides the much-needed high-level synthesis tools for Reference Flow 11.0, allowing our joint customers to quickly produce high-quality, TSMC-compliant hardware designs from a high-level SystemC description.”

Release 11.0 is the first generation of TSMC Reference Flow featuring electronic system level (ESL) design. Forte’s Cynthesizer v4.0 was included in the new flow to support SystemC high level synthesis.

Designers create abstracted models of their hardware using a high-level SystemC description. Cynthesizer processes the SystemC model, automatically creating the datapath and finite state machine. Designers can easily generate a number of candidate register transfer level (RTL) implementations by varying tool directives to specify latency, performance or area constraints.

Cynthesizer’s advanced algorithms and patented datapath optimization engine create high-quality building blocks tuned to the given TSMC library to minimize area and perform detailed timing analysis, eliminating timing closure problems inherent in typical RTL design processes. The design flow introduction based on Cynthesizer will be available on TSMC-Online.

“Joining TSMC’s Reference Flow marks a major milestone for Cynthesizer and for SystemC-based design,” concludes Sean Dart, Forte’s president and chief executive officer (CEO). “With a documented flow and methodology from SystemC to silicon, our mutual customers can be confident they will receive a high-quality implementation while addressing the complex issues of deep sub-micron design.”