Analysis
Exhibiting Advanced Chip Level Power Analysis, Optimization and Sign-off Solutions
Apache Design, Inc., a subsidiary of ANSYS today announced it will be sponsoring two complimentary Chip-Package-System (CPS) Workshops during DesignCon, at the Santa Clara Convention Center on February 1, in Santa Clara, California. These interactive sessions will bring together leading semiconductor companies and system houses to share their expert perspectives and best practices on chip and package modeling, and system-level verification for signal integrity, power integrity, electromagnetic interference and thermal. There is no cost to attend the workshops, but registration is required and seating is limited.
AbouThese in-depth technical sessions will provide designers with an open forum for exchanging the latest ideas and information on the most current technologies.
CPS Methodology for Cost-Down and/or Reliability – Session SS-200
This session features speakers from Intel and Cisco who will discuss how the performance and cost demands of today’s chip designs require a comprehensive chip-package-system approach to analysis. These industry experts will share their insights and expertise with case studies and real design examples for CPS convergence, and will discuss various aspects of analysis methodologies and technologies in terms of modeling, extraction and simulation. This session will take place on February 1, from 10:15 a.m. to 12:15 p.m. in Ballroom H.
CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications – Session SS-201
This session includes speakers from Micron, LSI and Xilinx who will focus on the challenges created by 3D stacked die and 2.5D Silicon Interposer with TSV chip designs. These leading technologists will examine modeling and simulation challenges in 3D-IC design and explore methodologies for power delivery network analysis, chip-to-chip communication, and thermal integrity using real case studies. This session takes place on February 1, from 2:00 p.m. to 4:00 p.m. in Ballroom H.