ErSt Electronic offers IP soft cores under the SignOnce license

The first set of cores implement the Advanced Encryption standard (AES, Rijndael) as described in the NIST (National Institute of Standards and Technology) Federal Information processing Standard (FIPS) Publication 197 document. The cores cover both encryption/decryption functions and key expansion, supporting any or all of the proposed key sizes (128/192/256-bit). All building blocks are implemented indivi
dually giving the user the greatest possible flexibility.

The cores feature a simple external interface and can be integrated into any AES design with minimum effort. The VHDL code is optimized for use in Xilinx FPGA technologies, achieving a data throughput of up to 2Gbps in Virtex-4 FPGAs. The needed slice area for a Spartan-3 FPGA ranges from 280 slices for an encryption core over 469 slices for a decryption core to 593 slices for a combined encryption/decryption core. The separate key expander requires another 244 slices. Alternatively, the round key schedules may be generated off-line and stored in internal RAM for subsequent use.

The deliverables consist of either fully synthesizable RTL VHDL code or NGC netlists for Xilinx FPGAs, together with a VHDL simulation model (test bench with FIPS test vectors and random tests) and user documentation.