Duo develop STT-MRAM testing module

This makes it possible to observe minute changes in the currents that flow through STT-MRAM memory cells, and is a step toward STT-MRAM failure analysis and eventually practical application of STT-MRAM technology via the development of a test system using the newly developed technology.

his testing technology is available for not only STT-MRAM but also other resistance change type memory such as ReRAM and PCRAM.

STT-MRAM memory cells consist of magnetic tunnel junctions (MTJs) and transistors, where memory cells are arranged in stacks to form memory arrays.

An MTJ is a nonvolatile memory element which utilises magnetoresistances to record data. In addition to not requiring standby power, STT-MRAM combines all the characteristics of high-speed operation, low-voltage operation, and high rewrite tolerance which are said to be difficult to achieve with other nonvolatile memory technologies.

Research institutions and companies all over the world are currently conducting STT-MRAM R&D.

For this emerging technology to be developed for volume production, highly efficient and accurate performance evaluation using memory test systems will be essential.

However, current switching in STT-MRAM is a probabilistic phenomenon which exploits the quantum-mechanical properties of electrons, and is subject to thermally induced fluctuations.

Additionally, these currents are very weak, at 100 microamperes or less, and flow only for nanoseconds at a time.

Therefore, even though measurement instruments can be used to measure switching on a single magnetic tunnel junction, or on one memory cell, it has been difficult to measure it on memory arrays containing multiple memory cells.

The Advantest- Tohoku University CIES collaboration developed a high-precision, high-speed current measurement module for an Advantest memory test system, which was used to conduct a successful experiment measuring minute changes in resistance and the variation distribution of current transition times during STT-MRAM switching operations, in units of nanoseconds.

In the experiment, an STT-MRAM test chip which composed of memory cells containing one MTJ and one transistor was prototyped on a 300mm silicon wafer—the standard size used in the industry—and the whole surface of the wafer was measured.

This success marks the development of a technology for analysing defects in STT-MRAM with high efficiency and high precision. It is hoped that it will lead towards improving yield rates and putting STT-MRAM into practical use.

The successful experiment was based on joint research by Advantest and the CIES Consortium, and the OPERA (Program on Open Innovation Platform with Enterprises, Research Institute and Academia) program*.

Tohoku University CIES will continue research and development activities aiming to commercialise a new STT-MRAM memory test system equipped with an external magnetic field application mechanism.

Picture shows an example of STT-MRAM switching current measurement. The current transition time during switching (the length of the horizontal axis in the figure, required to transition from a current value of I_Rap to I_Rp)

varies by switching operation. Minute differences, measured in microamperes and nanoseconds, were measured with this memory test system.

* OPERA is a program aimed at the formation of a platform for industrial-academic collaborations. Members include Tohoku University, Kyoto University, Yamagata University, and a group of advanced companies. Tohoku University acts as the coordinator of the program.