Deeply depleted channel & sub-threshold technologies for the IoT

For wearable and IoT devices superior energy efficiency is crucial: the conflicting requirements of increased miniaturisation along with longer battery life mean that standard CMOS technologies are reaching their limits and that solutions are urgently needed. Since the power consumption of digital circuits is proportional to the square of the supply voltage, low voltage operation is the best hope for significant improvements while maintaining NRE costs in check.

MIFS’ DDC technology enables fabrication of extremely-low-leakage transistors operating at supply voltages (Vdd) below 0.5V to obtain maximum power efficiency. DDC offers a better Vt mismatch & spread than conventional CMOS, allowing lower Vdd with minimum degradation of performance.

Applying DDC to 40/55nm CMOS along with mixed signal/RF and embedded NVM allows cost-effective and highly integrated analog and RF SoCs for IoT /wearable platforms. MIFS has now joined forces with CSEM, with their long design experience in low-voltage, low-power integrated circuits, to develop an ultra-low power IP platform targeting near/sub-threshold supply voltages in the MIFS DDC technology. The goal is to develop a best-in-class Extreme-Low Power (ELP) platform with the associated ecosystem to enable chip designs for energy-critical wearable and IOT devices.

“MIFS DDC technology offers best-in-class low voltage and low leakage operation. By working with CSEM we will be able to develop an ecosystem to make the benefits of this technology available widely to our partners”, says Masahiro Chijiiwa, Director and Corporate Senior VP, MIFS.

Alain-Serge Porret, Vice President of Ultra-low-power Integrated Systems, CSEM, adds “The partnership with MIFS is fully aligned with CSEM’s long-standing commitment to ULP design. We are thrilled to soon be able to add DDC-based IPs to our portfolio of solutions, allowing us to reinforce our offer of ultra-low power design services & IPs”.

The development will be performed in close direct collaboration between process engineers, library specialists and ULP design experts, both in Japan and Europe, in order to unleash the full potential of the platform, which is expected to be available for limited release in Q4 2016.