Configurable System-on-Chip ICs from STMicroelectronics

8th March 2007

ES Admin

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STMicroelectronics has announced two new additions to its SPEAr family of configurable System-on-Chip ICs. The dual-core SPEAr Plus600, complemented with a single-core variant, SPEAr Head600, represents a market-unique solution that enables printer, fax, point-of-sale (POS) and other equipment manufacturers to develop complex yet flexible digital engines at a fraction of the time and cost required by a full-custom design approach. Additionally, the possibility to choose between a single- and a dual-processor device with the same footprint and architecture will enable manufacturers to address different market segments for the same application.

“No other product in this market combines low investment costs and short time to market with flexibility and customizability that ST’s SPEAr chips can provide,” said Vittorio Peduto, General Manager of ST’s Computer Systems Division, Computer Peripherals Group. “With these products, ST is providing its customers with an unprecedented feature set, connectivity and computing power, and allowing them to address the full market from high-end to low- and mid-range models using the same architecture and software stack.”

Manufactured in 90nm process technology, ST’s new SPEAr SoCs integrate one or two advanced ARM926 processor cores with 16k (data) + 16k (instruction) of cache memory running at 333MHz (worst case conditions) and 600,000 gates (ASIC-equivalent) of embedded configurable logic, complemented with memory interface supporting DDR/DDR2 memories and a large connectivity IP (intellectual property) portfolio.

The DDR/DDR2 memory interface is compatible with DDR2-666 (333MHz) memories, allowing the same physical pins to drive DDR or DDR2 memories. The connectivity IP includes an IrDA interface supporting fast IrDA, Gigabit Ethernet MAC and three USB2.0 ports (1 device and 2 hosts). The new set of features also includes a XGA LCD controller supporting up to 1024x768-pixel resolution in true color (24-bit) and a JPEG codec.

Additionally, ST’s designers paid special attention to electromagnetic compatibility (EMC) by using a dithered PLL with programmable frequencies and jitters and LVDS I/Os operating up to 600MHz for high-speed communication links. Libraries of IP and hardware accelerators are available to be embedded in the configurable logic. The devices include 136 Kbyte of SRAM and 32 Kbyte of ROM completely available for customers’ applications.

With the dual-core SPEAr Plus600, customers can run two different operating systems on the same chip. This enables, for example, the integration of the typical functions of a multifunction printer or copier on a single chip: Linux, or a similar complex operating system, runs on one processor, handles connectivity and system management, while a RTOS (Real-Time Operating System) on the second processor manages control functions, such as motor control or timing of critical interfaces. This flexibility also allows a processor to function as an accelerator coprocessor for critical image functions. A dual-core solution also allows designers to use a common software stack, developed on one processor, and implement upgrades or additional features on the second processor.

Both the SPEAr Plus600 and the SpearHead600 come complete with a dedicated development board that allows developing and testing of the customer system with minimum time and resource requirements. By using an external FPGA that mirrors the SoC’s internal configurable logic block, designers can proceed with the software and hardware development without waiting for the final validation. Once the customer SoC passes the functional qualification, full production can ramp up in eight weeks’ time from the final RTL availability.

Both devices will start sampling for high-volume OEMs by the end of March 2007. The price is $12 for the SPEAr Plus600 and $10 for the SPEAr Head 600, in quantities of 20,000 pieces.