CMOS retimer with EDC brings 10G Ethernet performance to legacy fibre infrastructure

Combining clock data recovery (CDR) and a fully automatic EDC circuit, the highly integrated PHY2060 greatly simplifies optical module design. The chip’s internal algorithms remove the need for complex microcontroller support and thereby substantially reduce product development time.

A shorter bill of materials, combined with the IC’s miniature 36-pin, 5mm x 5mm flip-chip BGA packaging, means greater design flexibility for developers of ultra small form factor optical modules. Port densities can be substantially increased, while total module cost can be significantly reduced.

To simplify product evaluation and qualification the PHY2060 also includes a PRBS generator and a BER detector, enabling comprehensive end-to-end link testing. On boot-up the device automatically selects between the chip’s 2-wire or serial peripheral interfaces.

Phyworks’ proprietary, fully LRM compliant EDC technology is regarded as the industry’s most cost effective solution for overcoming modal dispersion in multimode fibre LAN infrastructure and achieving reliable 300m link lengths.

PHY2060 samples and an evaluation board are available now through Phyworks’ regular distribution channels.