Christian Ott of SEHO Systems to Offer Void Reduction Tips at SMTA 2012

Voids in solder joints represent one of the primary problems, especially for power electronics. A low and homogeneous thermal resistance of solder joints is demanded for a quick and uniform conduction of the heat loss from the power chip. The same applies for the electrical conductivity of solder joints. Enclosed voids can cause a displacement of electrical and thermal paths as well as a local concentration of power and heat. Additionally, gas voids are quick to form spheres in the solder gap, which could be a cause for tilting of chip components and a wedge-shaped solder gap. This is tightening the problem of patchy distribution of current or heat and is causing stress and cracks.

Voids in solder joints are nearly inevitable for common process conditions. The ingredients of the solder pastes, which evaporate during the soldering process, cannot exhaust completely, especially for plane solder joints and closed gaps, and will be enclosed in the solder joints. With the introduction of lead-free solders with the well-known difficulties of poor wetting and smaller process windows the problem has become more acute. Therefore, the acceptable or established maximum void content can exceed frequently. This presentation will discuss a new process technology that should produce relief for that.