Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool

”ESL synthesis offers our design community the next great leap in productivity. Much like the move to RTL years ago, the move to higher levels of abstraction based on C and SystemC offers the promise of better quality of results in a shorter amount of time. By combining the market leading products in C synthesis, sequential verification, and power optimization within Calypto, we will be the only company capable of delivering a fully integrated flow, and delivering on that promise of ESL,” said Doug Aitelli, Chief Executive Officer of Calypto Design Systems. “In addition, we remain fully committed to our existing high level synthesis partnerships and to industry-wide interoperability.”

“This is a great deal for Calypto,” said Gary Smith, Chief Analyst at GSEDA. “They are clearly one of the companies on the rise in ESL, and this gives them the chance to offer a compelling power-optimized C to RTL flow if they can integrate all the pieces.”

ESL methods allow designers to work at a higher level of abstraction, greatly reducing errors and allowing greater optimization of integrated circuits (IC) in key attributes like speed and power. To adopt ESL methods, designers need to have confidence that tools, as they translate from the higher level of abstraction to lower levels, don’t introduce errors. Typically, designers have used extensive RTL verification to ensure that no errors have been introduced.

SLEC System-HLS uniquely addresses this challenge with C to RTL formal equivalence checking using patented sequential analysis technology to create an easy to use synthesis and verification flow environment. Designers can perform comprehensive functional verification using SLEC System‐HLS to formally verify equivalence between SystemC ESL models and RTL implementations. This leads to up to 100x speed up times in RTL verification as it removes the need for significant and time consuming RTL simulation to validate that the RTL matches the C or SystemC source. Tight integration between Calypto’s SLEC System-HLS and Catapult C Synthesis will give designers confidence that the IC they designed in C or SystemC is the IC that is being delivered in RTL.

Additionally, the PowerPro SoC Power Reduction Platform can do RTL level power optimizations. Added to the Catapult C Synthesis and SLEC System-HLS hardware realization flow, this allows designers to swiftly go from C and System C designs to power-optimized RTL.

“We remain deeply committed to ESL. We view this transaction as an innovative way to accelerate adoption of ESL methodologies, to strengthen our partnership with Calypto, and as one that complements our continued investment in ESL virtual prototyping environments led by our Vista product,” said Brian Derrick, vice president of marketing at Mentor Graphics. “Calypto’s Sequential Logic Equivalency Checker is a critical and unique technology for enabling the adoption of ESL. Its combination with the market-leading Catapult C Synthesis product and the PowerPro SoC Power Reduction Platform, should give designers the confidence to adopt ESL methods and enjoy the significant benefits that designing at higher levels of abstraction brings.”

Current customers of the Mentor Graphics Catapult C Synthesis tool will continue to be supported by Mentor Graphics. Moving forward, any new customer sales and support will be supplied by Calypto.