Cadence Virtuoso Accelerated Parallel Simulator Wins Elektra Electronics Industry Awards 2010

“The entries in this category were very strong this year, but the judges felt the winner’s software tool could make a real impact on design cycles,” commented Richard Wilson, editor of Electronics Weekly and chairman of the judges.

The Virtuoso Accelerated Parallel Simulator (APS) addresses the challenges analog, mixed-signal, and RF designers face: accuracy degradation of results, excessive simulation run times and huge learning curve for setup and post processing. APS is part of the Virtuoso Multi-mode simulation platform - developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, for both pre- and post-layout designs.

“It is an honor to receive this award,” said David Desharnais, group director of product management at Cadence. “APS is a key element of Silicon Realization,which was outlined in the EDA360 vision. It enables our customers to boost productivity and provide unmatched performance for verification of very complex analog and mixed-signal IC designs.”