Cadence to Showcase Latest Verification Tools and Methodologies at DVCon 2013

Visitors to the Cadence booth (#1102) can learn about verification at the IC, SoC and system levels and the company’s latest advances in verification IP.

Additional Cadence participation:

-A lunch panel, at noon Feb. 27 in the Pine/Cedar Ballroom, on “Best Practices in Verification Planning,” moderated by John Brennan of Cadence and featuring panelists from Xilinx, Maxim Integrated Products, Verilab, Paradigm Works, Oski Technology, and Cadence.
-An industry leaders panel, at 3:30 p.m. Feb. 27 in the Oak/Fir Ballroom, titled, “The Road to 1M Design Starts,” featuring Ziv Binyamini, Cadence corporate vice president, Systems and Software Solutions.
-A Cadence-led session from 8:30 a.m. to noon Feb. 28, in the Donner Ballroom, titled, “Fast Track Your UVM Debug Productivity with Simulation and Acceleration.”