Cadence to Showcase Advanced FinFET Design Technology at Common Platform Technology Forum 2013

Attendees can learn more about 20-nanometer and 14-nanometer FinFET standard cell and IP design, physical implementation, and extraction, timing and power signoff, as well as recent 14-nanometer tapeouts in which Cadence was involved.

In addition, Dr. Vassilios Gerousis, distinguished engineer and technologist at Cadence Design Systems (NASDAQ: CDNS), will join engineers from IBM Research to present: “Next-Generation R&D and Advanced Tools for 14-nanometers and Beyond.” Gerousis will be joined by Dr. Mukesh Khare, director of Semiconductor Technology Research, and Dr. Supratik Guha, director of the Physical Sciences Department.

WHERE:

-Cadence will be at Booth #401 in the Pavilion at the Santa Clara Convention Center
-Gerousis’ presentation will be in the Mission City Ballroom

WHEN:

-The Cadence booth will be open Feb. 5 from 11:30 a.m. to 6 p.m.
-The presentation will be Feb. 5 from 3:50 p.m. to 4:50 p.m.