Cadence to aquire Forte Design Systems

Due to increased IP complexity and the need for rapid retargeting of IP to derivative architectures, the high-level synthesis market segment has grown beyond early adopters toward mainstream adoption, as design teams migrate from hand-coded RTL design to SystemC-based design and verification. With this aquisition, Cadence will add Forte’s synthesis and IP products to the Cadence C-to-Silicon Compiler offering. This will enabe Cadence to further drive a SystemC standard flow for design and multi-language verification.

Forte delivers QoR for datapath-centric designs, world-class arithmetic IP, valuable SystemC IP and IP development tools. Forte’s Cynthesizer HLS product features strong support for memory scheduling, especially for highly parallel or pipelined designs. These strengths complement the high QoR for transaction-level modeling, under-the-hood RTL synthesis and incremental ECO support featured by Cadence C-to-Silicon Compiler.

“Growth in the high-level synthesis market segment is accelerating”, explained Charlie Huang, senior vice president of the System & Verification Group and Worldwide Field Operations at Cadence.  “HLS tools are now addressing a broader application space and producing equal or better quality of results than hand-coded RTL, fueling worldwide adoption and production deployment amongst leading companies. We look forward to welcoming Forte’s technology and skilled team to Cadence to help address this opportunity.”

“Cadence and Forte have compatible approaches to high-level synthesis, and a similar vision to enable migration of design to the system level,” commented Sean Dart, CEO of Forte. “The combination will benefit customers through a standardized system-level flow, improved product capabilities for both customer bases, and integration all the way to silicon.”