AppliedMicro Introduces Multi-core System-on-Chip

The APM 83290 includes a processor subsystem that integrates two Titan cores based on Power Architecture technology, delivering frequencies of 1.5 GHz per core. The Titan core is a superscalar, dual-issue, out-of-order core designed to achieve industry leading single thread performance on a per clock basis. Along with high performance, innovative circuit design techniques enable the APM 83290 to deliver speeds of 1.5 GHz in 90nm bulk CMOS while comparable designs require 45nm SOI process technology to achieve similar operating speeds. This combination of performance and price flexibility makes this solution attractive for many low cost application areas that traditionally were not serviced by Power Architecture products.

The APM 83290's PacketPro consists of a number of acceleration blocks designed to offload the processor subsystem from commonly occurring tasks in networking applications. A fundamental component of PacketPro is a message passing architecture that simplifies data movement between the various acceleration blocks and provides Quality of Service guarantees for each flow regardless of the loading from other flows. This Quality of Service is guaranteed via a powerful and flexible Queue Manager and Traffic Manager (QMTM) block. Instead of using isolated operation offloads, the acceleration blocks are designed to offload entire protocol level tasks in order to reduce processing overhead and increase application performance. These blocks are fully software programmable in order to support proprietary features and provide upgradability for future protocol enhancements.

Instead of simply throwing extraneous general purpose CPU cores into a chip, we've developed dedicated silicon blocks to offload the most challenging system tasks and ensure that the APM 83K family of SoCs delivers more efficient power/performance ratios for our customers' applications, said Robert Fanfelle, Associate Vice President of Strategic Marketing for AppliedMicro. PacketPro technology enables efficient packet processing and fair sharing of bandwidth amongst flows allowing our powerful multi-core processor subsystem to concentrate its resources on executing customer applications.

AppliedMicro's MultiEase(TM) technology allows customers to reduce development efforts and accelerate their time to market schedules by providing virtualization of on-chip resources, fault isolation debug and error recovery. This allows customers to easily migrate applications originally developed for single core microprocessor systems into a multi-core environment. In addition, the APM 83K series is code compatible with PowerPC(TM) products, giving developers the flexibility to leverage their software development efforts and tool sets into new multi-core applications.

Our customers have put many years into fine tuning and honing their software for single-core environments and they want to preserve their investment yet still take advantage of next generation multi-core processors, Fanfelle said. With MultiEase, our customers can avoid having to fundamentally redesign their software simply to work in a multi-core shared-resource environment. The customer can ease his transition by controlling the amount of resource sharing and optimization for their particular mix of applications, in turn improving product reliability and time-to-market.

Converged network applications represent a rapidly growing portion of today's $3.3 billion high-speed embedded processor market, said Linley Gwennap, principal analyst of The Linley Group and coauthor of a new report on embedded processors. AppliedMicro has extensive experience with packet processing, which is a key function for processors in these networking applications. The APM 83K series with PacketPro is company's best effort yet for combining its embedded processor technology with its networking experience, giving AppliedMicro an advantage in this large and growing market.

The hardware features of the APM 83290 SoC include dual Titan cores, each with a floating point unit, 512KB of shared L2 Cache memory with ECC support, full hardware memory and I/O coherency, 64-bit DDR2 SDRAM interface, security acceleration for IPSec, SSL, Kasumi, SNOW3G and public-key protocols. Other features include a classification engine, multi-channel DMA engine, and high speed interfaces for Gigabit Ethernet ports, IEEE1588v2 support, PCI Express(R) v2.0, Serial RapidIO(R), USB and SATA.