Altera's Stratix IV FPGAs Pass Interlaken Interoperability Test

Altera passed interoperability testing using a Stratix IV GT FPGA development board along with Altera's internally developed Interlaken intellectual property (IP) core. The IP core is fully compliant to the Interlaken Protocol Definition revision 1.2 and provides a cost-effective, risk-free solution that can be quickly implemented in the FPGA.

“The Interlaken protocol is a popular solution for equipment manufactures due to its ability to enable high-speed chip-to-chip packet transfers and Altera is committed to providing our customers a comprehensive Interlaken solution through our leading-edge FPGAs,” said Luanne Schirrmeister, senior director of component product marketing at Altera Corporation. “By offering an Interlaken solution that supports data rates up to 10-Gbps, Altera is driving the industry's move toward 100G systems.”

Passing the Interlaken Interoperability Test

The Interlaken Alliance's device interoperability test included five chip vendors testing the connectivity between their components using the Interlaken protocol. Altera successfully demonstrated interoperation with all the participating ASSP vendors' solutions, including Cortina's CS1999 and CS3477 device families and PMC-Sierra's HyPHY 20G platform.

“As demand for voice, video, and data increases, service providers are looking for ways to upgrade their existing infrastructure,” said Fred Olsson, product line director at Cortina Systems. “Proven interoperability between the Altera Interlaken IP core on Stratix IV hardware and Cortina's CS1999 40Gb/s framer as well as CS3477 aggregator ICs enables not only a seamless connection for high throughput packet processing but also further demonstrates Interlaken's ability to eliminate bandwidth restrictions and increase performance for communications applications that require the highest possible performance.”