Altair reduces development-cycle turnaround time by 20%

Altair utilised the Palladium XP platform to accurately model the register-transfer level (RTL) design running with software and flash memory, enabling them to capture half of all hardware and software bugs in a pre-silicon environment. This reduces the development-cycle turnaround time by 20% compared to their previous process. LTE software development for L1, L2 and L3 protocols was completed and verified in the hardware context three to four months before silicon availability.

“As the IoT expands beyond consumer devices to include all types of connected ‘things,’ high-performance, ultra-low-power silicon solutions enabling these connections become key,” said Eli Zyss, Vice President of Silicon Design, Altair Semiconductor. “Recently we deployed the Palladium XP platform to address the design and verification challenges of our next-gen IoT and broadband LTE silicon development. This allowed us to shorten the development cycle, improve turnaround-time, and address hardware and software issues pre-silicon.”