Rail to Rail Comparators Support all Prevailing Digital Output Stages including LVDS

The LVDS-compatible output stage, designed to drive any standard LVDS input, allows the ADCMP60x comparators to be coupled with FPGAs (field programmable gate arrays) and ASSPs (application-specific standard products) that feature high-speed inputs and achieve faster transition times.

The ADCMP60x family offers propagation delays ranging from 1 ns (nanosecond) to 35 ns with as little as 2.5 pico-second rms random jitter. The ADCMP60x comparators offer rail-to-rail performance that is fully specified from 2.5 V to 5.5 V. This is particularly beneficial at low voltages where previous generation fast rail-to-rail comparators experience dead zones at operating voltages below 2.7 V.

Isolating the input and output supplies is important because parasitic coupling from the output to the input can cause instability when overdrive conditions are low. Several members of the ADCMP60x family split the two supplies to provide a wide input signal range and reduce power consumption by as much as 50 percent compared to competitive offerings. High-speed latch and programmable hysteresis features are provided in a single-pin control option, producing balanced input-to-output delays and eliminating oscillation issues.

The ADCMP60x comparators work well in applications with Analog Devices’ family of DDS (direct digital synthesis) products to generate programmable high-speed, low-jitter clocks. They also complement ADI’s high-speed log amps, such as the AD8318, for amplifying low-level RF burst pulses.


The ADCMP60x comparators are sampling now and will be available in full production quantities in September of 2006. Priced from $0.58 to $2.35 in 1,000-piece quantities, the comparators are available in SC-70 (small outline transistor plastic packages), SOT-23 (small outline transistor packages) and MSOP (mini small outline plastic packages) and LFCSP (lead-frame chip scale packages).