Home > Products > Lowest Power, 16-Bit, 80Msps ADC Reduces Noise in Data Conversion Systems

Mixed Signal/Analog

Lowest Power, 16-Bit, 80Msps ADC Reduces Noise in Data Conversion Systems

30th March 2010

ES Admin

0 0

Datasheet

Linear Technology Corporation introduces a low-power 16-bit no missing codes, 80Msps analog-to-digital converter (ADC) that dissipates only 89mW, less than half the power of competing 16-bit solutions. The LTC2259-16 provides a pin-compatible upgrade to the existing LTC2259-14 family of 14-bit low power ADCs, offering the lowest power dissipation for a single 16-bit ADC with double data rate (DDR) CMOS/LVDS outputs. In addition to offering significantly lower power, the LTC2259-16 integrates two useful features for reducing digital feedback, including alternate bit polarity (ABP) mode and a data output randomizer. These features, in combination with low power, ease the task of designing with high speed ADCs in a wide variety of applications, including HD broadcast cameras, IMO radar, Ethernet testers, portable test and instrumentation, software-defined radios and cellular basestations.

Digital feedback occurs when energy from ADC outputs couples back into the analog section, causing interaction that appears as odd shaping in the noise floor and spurs in the ADC output spectrum. The worst situation is at mid-scale, where all outputs are changing from ones to zeroes, or vice versa, generating large ground currents that couple back into the input.

To combat this effect, the LTC2259-16's proprietary alternate bit polarity (ABP) mode inverts all of the odd bits before the output buffers to equalize the number of ones and zeroes switching. This method effectively cancels the large ground plane currents that contribute to digital feedback. In addition to the alternate bit polarity mode, an optional data output randomizer is also available for reducing interference from the digital outputs. The randomizer decorrelates the digital output to reduce the likelihood of repetitive code patterns that couple back into the ADC input, causing unwanted tones in the output spectrum. Both digital feedback reduction techniques improve spurious free dynamic range (SFDR) performance by 10-15dB.

Operating from a low 1.8V analog supply, the LTC2259-16 offers signal to noise ratio (SNR) performance of 73.1dB and SFDR of 88dB at baseband. Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance. The LTC6406 is a recommended rail-to-rail ADC driver for maintaining LTC2259-16's AC performance.

The LTC2259-16's digital outputs can be set to full rate CMOS, DDR CMOS, or DDR LVDS. Double data rate digital outputs allow data to be transmitted on both the rising edge and the falling edge of the clock, reducing the number of data lines needed by half. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

Offered in a 6mm x 6mm QFN package, the LTC2259-16 includes a clock duty cycle stabilizer circuit to facilitate non-50% clock duty cycles, programmable digital output timing, programmable LVDS output current and optional LVDS output termination. These features combine to make the data transmission between the ADC and the digital receiver more flexible.