Micros

Renesas Technology Releases Microcontrollers with 1 Mbyte On-Chip SRAM for Digital Audio and Graphical Dashboard Applications

12th May 2008
ES Admin
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Renesas Technology Corp has announced a total of eight new product versions of the SH7262 and SH7264 high-performance 32-bit microcontrollers with 1 Mbyte of on-chip SRAM for digital audio and graphical dashboard applications. Sample shipments will begin in August 2008 in Japan.
Part of the SuperH Family of 32-bit RISC microcontroller/ microprocessor, the SH7262 and SH7264 belong to the SH7260 Series of microcontrollers for digital audio applications. A full 1 Mbyte of SRAM, which can be used in place of external synchronous DRAM (SDRAM), is integrated on-chip. This makes it possible to provide more powerful graphics functions for graphical dashboard systems or TV display functions in midrange and low-end products largely using a single chip. A full complement of peripheral functions is provided within specifications designed to keep costs down for a high cost-to-performance ratio. The maximum operating frequency of 144 MHz enables faster operation in applications such as equipment control or digital audio signal processing.



The SH7262 has a 176-pin QFP package, and the SH7264 has a 208-pin QFP package. Their main features are summarized below.



(1) No need for external SDRAM thanks to industry top-class 1 Mbyte of on-chip SRAM

An ample 1 Mbyte of on-chip SRAM is provided for video display use. It can be configured as a frame buffer to store video data temporarily, which is necessary when implementing graphical display capabilities. The generous SRAM capacity means that it is possible to use a TFT LCD panel display up to WQVGA size (480 × 240 pixels) without the need for external SDRAM as video memory. This helps reduce the total number of system devices and contributes to a more compact design. (In this example, the on-chip SRAM can be used as a frame buffer capable of storing up to two screens.) Alternately, the on-chip SRAM can be employed to store programs or data.



(2) Reduced system cost due to numerous peripheral functions, including new graphical display functions

The SH7262 and SH7264 provide a new video display controller and digital video input pins for use with graphical and video display applications. It supports functionality such as video recording, size reduction, alpha blending effects (superimposition of transparent or semitransparent images), and superimposition of video input. Digital RGB output pins allow output of images or video in RGB565 format (in which each color is represented by 16 bits: 5 bits for the red [R] component, 6 bits for green [G], and 5 bits for blue [B]) at up to WQVGA size. This on-chip functionality makes it possible to develop products, such as car information systems with rear-view or side-view camera display and midrange or low-end graphical dashboard systems, using fewer devices and at lower cost.



In addition, a 16-bit external data bus supports direct connection to external memory, such as flash ROM, SDRAM, or SRAM, without the need for external parts. New peripheral functions include a motor control PWM timer, which can control the display of up to four gauges, and a decompression unit for decompressing video data. Among the peripheral functions continued from earlier products in the SH7260 Series are the CAN*2 interface, USB 2.0 Hi-Speed specification host/function capability, and audio signal processing. These compose a full complement of peripheral functions and interfaces required by midrange and low-end digital audio products or graphical dashboard systems. The SH7262 and SH7264 make it possible to build a system largely using a single chip, since the only additional device needed is external memory to store programs. They help to reduce system cost and shorten the system development time.



The SH7262 and SH7264 are built around the SH2A-FPU CPU core (which incorporates an FPU), have a maximum operating frequency of 144 MHz, and deliver excellent processing performance. The instruction set of the SH2A-FPU is backward compatible with the SH-2A and SH-2 CPU cores, allowing developers to reuse program code created for earlier products. In addition, ROM code efficiency has been improved approximately 75% in comparison with the SH-2. As a result, the object code for the same program can be compressed to about three-quarters the previous size, conserving the memory capacity available for storing programs.



This combination of excellent signal processing performance and ROM code efficiency means that compression and decompression of audio data in formats required by digital audio applications, such as MP3, WMA, or AAC (Advanced Audio Coding), is performed more quickly and program sizes are reduced. Thanks to the newly added large-capacity SRAM, not only processing tasks related to equipment control and digital audio, but also video display capabilities can be implemented on a single chip. This reduces the total number of devices required and helps lower both the cost and the power consumption of the system.

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