Zero capacitor memory technology proved realisable on FinFET/TriGate device geometries

Z-RAM memory arrays have already been successfully demonstrated on silicon using partially depleted SOI structures, and the experimental results presented in ISi’s new paper ensure that the technology will scale to 45nm and beyond.

In the recently-introduced Z-RAM floating body memory cell, the conventional storage capacitor is replaced by the body capacitance of a SOI MOSFET. The charge stored in the floating body affects the device threshold voltage through the body effect and can be used to distinguish two states. This eliminates the need for a capacitor element, so the resulting memory cell structure is based solely on a single transistor. Therefore, Z-RAM memories can achieve five times the density of embedded SRAM and twice the density of embedded DRAM designs.

For the first time, new experimental work by ISi – presented in the IEEE paper co-authored by ISi’s CTO Pierre Fazan and personnel from TI, Infineon, SOITEC and ATDF (a subsidiary of Sematech) – shows that good retention characteristics for a Z-RAM memory cell based on CMOS FinFET and Tri-Gate devices can be measured. This means that FinFET-based Z-RAM memories are manufacturable, enabling the production of very low cost DRAMs and eDRAMs for 45 and sub 45-nm generations.