Flash memory embedded process based on 65nm logic process

The IoT market is seeing strong demand for low power consumption in areas including wearable and healthcare-related equipment. In response, Toshiba has adopted Silicon Storage Technology’s 3rd gen SuperFlash cell technology, in combination with its own 65nm logic process technology. The company has also fine-tuned circuits and manufacturing processes in developing an ultra-low power consumption flash embedded logic process. MCUs for consumer and industrial applications that apply the process can lower power consumption to approximately 60% that of current mainstream technology.

Following the first series of MCUs, Toshiba plans to release sample BLE products in fiscal year 2016. The company also plans to apply the 65nm process to its wireless communication IC product family that can optimise use of low power consumption characteristics, including NFC controllers and contactless cards.

As well as low power consumption advantages, the process technology contributes to shorter development time, as application software can be easily written and rewritten to flash memory during development. By engineering advances in devices offering ultra-low power consumption to promote further development of specialised flash peripheral circuit technology and of logic and analogue circuit technology, Toshiba will meet continuing growth in demand for low-power applications.

The company aims to lower power consumption for entire systems, targeting 50μA/MHz operation, and to develop innovative products for IoT. In applications where significant cost reductions are a concern, Toshiba has developed an NVM embedded process that adopts Yield Microelectronics Corporation’s single-poly MTP cells on Toshiba’s 130nm logic process technology.

NVM and analogue circuits are embedded on a single chip that can incorporate multiple functions conventionally executed by a multi-chip system. This reduces the number of terminals and realises smaller packages. Applying MTP specifications for write times improves the process’s performance while limiting increased steps in mask pattern lithography to three or fewer and even none. By using MTP to adjust output accuracy, Toshiba will expand its product line-up in fields where higher accuracy is essential, such as power management ICs.