Tiempo selects IC'Alps for silicon implementation

Tiempo Secure’s TESIC includes a secure MCU, secure cryptographic processors and hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. While TESIC is already available on multiple silicon processes, including GF 55 and TSMC 40, the hard macro is now implemented by IC’Alps in GF 22 and TSMC 16 – with some other technology nodes considered in the coming months.

“By collaborating with IC’Alps for back-end implementation, Tiempo is now able to provide its customers with a wider choice in terms of technology,” said Serge Maginot, CEO of Tiempo Secure.

Serge Maginot said IoT applications are driving the demand for a new generation of Secure Elements. Indeed, with billions of IoT devices deployed, it is becoming crucial to secure our connected world with innovative and easy to implement solutions that protect sensitive data from external attacks. Tiempo Secure’s TESIC addresses this security concern with a tamper resistant hard macro designed for plug-and-play MCU or SoC integration. TESIC is delivered to the certified fab, with the guarantee chips integrating this macro will pass CC EAL5+ PP0084 and/or EMVCo security certifications.

“We are extremely proud to be partnering with Tiempo Secure,” said Jean-Luc Triouleyre, CEO of IC’Alps. “We see a growing trend toward closer ties between IP developers and Design Houses. One reason is that few companies can afford the large investment in EDA software needed for physical implementation tasks.”

The company offers customers the flexibility to choose an entry point into the ASIC/SoC implementation flow according to their needs, turnaround time, expertise and available EDA environment.