embedded world 2024: Codasip demonstrates CHERI memory protection

The technologies are enabled by Codasip's Custom Compute offering combining the Codasip Studio design automation tools with a range of customisable RISC-V processor IP.

Codasip will showcase its Custom Compute offering in hall 4, stand 4-368. Visitors will get to see fine-grained memory protection with CHERI. This technology, invented at Cambridge University and brought to commercial implementations by Codasip, actively prevents the most common cyber-attacks with the potential of eliminating approximately 70% of vulnerabilities documented in the Common Vulnerabilities and Exposures (CVE) program. As announced in October 2023, Codasip is adding built-in fine-grained memory protection to its recently launched 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions.

In addition, the company will show how to profile an embedded application to identify bottlenecks in the code and how custom instructions can be easily added to optimise the hardware to improve the application's performance. Examples of the potential gains from HW/SW co-optimisation include:

• 2x performance gain running the SHA512 cryptographic hash algorithm
• 2.5x speedup and 30% reduction in power consumption for AI/ML workloads

As part of the embedded world conference programme, Codasip’s CTO Zdenek Prikryl will present the session ‘Customised RISC-V in a simple game console’ (Session 8.5 SYSTEM-ON-CHIP (SoC) DESIGN / RISC-V 2) on Thursday 11 April.