Cadence receives TSMC OIP award for N3 collaboration

Cadence’s Yufeng Luo, Vice President, R&D in the Digital & Signoff Group, presented the paper, highlighting how engineers creating hyperscale and mobile designs can successfully benefit from the performance and efficiency of the TSMC N3 process technology and the Cadence digital full flow.

The paper won the award based on the popular vote by conference attendees. Attendees had an opportunity to learn about new design techniques available with the N3-certified Cadence digital flow, which includes several feature enhancements—EUV layer support, route and via rules, cell placement, routing congestion avoidance, on-chip variation (OCV) accuracy and new signoff design rule checking (DRC) tools—to name a few.

“The Cadence digital full flow has been continuously optimised to support advanced N7, N6 and N5 production designs and now also supports TSMC’s latest N3 process technology,” said Cadence’s Luo. “This recognition further indicates our commitment to collaborating with TSMC to facilitate advanced-node design, and we look forward to seeing our mutual customers achieve success with our digital full flow and TSMC’s N3 process technology.”

“The Cadence paper presented at TSMC 2020 NA OIP Ecosystem Forum was an insightful overview as to how designers can achieve optimal power and performance using the latest Cadence and TSMC technologies,” added Suk Lee, Vice President of the Design Infrastructure Management Division at TSMC. “Enabling our customers to reach new milestones with mobile and hyperscale design development is the greatest reward that comes from our continued collaboration with Cadence.”