Wafer-level System-in-Package for IoT applications

Therefore, NXP proposes a simple but smart combination of SiP and PoP integration with very small form factor for IoT applications.

“NXP’s module is a demonstration of emerging advanced packaging technologies such as FO PoP SiP,” commented Jérôme Azémar, Technology & Market Analyst at Yole Développement (Yole), sister company of System Plus Consulting. “With this design, NXP distinguishes it from other companies. NXP, in collaboration with its historic partner Nepes, is clearly showing its strategy focused on the integration of several chips to create a module with higher added-value.”

NXP’s module has been initially developed for simple IoT applications. However, tomorrow, this SiP approach might be intended to high-end market segments.

System Plus Consulting proposes today a relevant reverse engineering and costing analysis dedicated to NXP FO PoP SiP, titled NXP SCM-i.MX6 Quad High Density Fan-Out Wafer-Level System-in-Package report. This analysis includes a complete review of PoP SiP solution, featuring die analyses, processes, and package cross-sections. It also includes a comparison with competitive solutions: TSMC’s inFO and Shinko’s MCeP PoP technology. System Plus Consulting report contains a complete cost analysis and a selling price estimation of the system.

In several applications, SiP integration of several devices with a very small form factor has become a huge challenge. Emerging markets like the IoT bring new system configurations looking for low power consumption and high performance. NXP has therefore brought in a tiny wafer-level SiP, an application processor that has been well-proven in automotive applications, a PMIC and a boot memory based on flash technology. Its footprint is about half the size of a discrete implementation on standard PCB.

Fully dedicated to IoT applications, NXP’s module includes the i.MX6-Quad application processor, MMPF0100 power management system, a 16MB Flash memory and about 100 surface mounted devices, all in a single package smaller than 200mm³.

“This is the first multi die fan-out device than we have found in the market, and could be a key milestone for fan-out SiP technology,” asserted Stéphane Elisabeth, Advanced Packaging & RF Cost Engineer at System Plus Consulting.

The system uses non-conventional wafer-level packaging developed by Nepes. It has innovative interconnections, enabling a PoP configuration with Micron’s SDRAM memory chip. A custom redistribution device, called Via Frame, allows memory stacking. These components are integrated in EMC on few RDL.

“Powered by the NXP i.MX6 Quad application processor and enabling PoP configuration, the SCM-i.MX6Q is extremely power efficient,” commented Stéphane Elisabeth from System Plus Consulting. This makes it suitable to reduce product time to market by simplifying the high-speed memory design and significantly reducing the overall design complexity of the processor/PMIC/memory sub-system. Thanks to the redistributed chip packaging technology applied to this SiP, NXP has realised a complete, very small, low-power, high performance solution.

What will be the next step? According to Yole’s analysts, FO remains the highest growing advanced packaging platform with a 36% CAGR between 2016 and 2022 (in revenues). System Plus Consulting and Yole are convinced that FO SiP will strongly penetrate the market in a near future. And Apple’s processor, A11 in the future iPhone8 is a good example. Both partners will so pursue their investigation to analyse emerging technologies and make the link with the market evolution and the strategy of leading advanced packaging companies.