Synchronous Mobile Multimedia Interconnect is industry first says IDT

The M2I is designed to work with application processors and baseband processors that make use of an address-data mux (ADM) interface. The ADM interface has a lower input/output (I/O) count and higher bandwidth than other approaches, such as the standard, asynchronous dual-port RAMs and embedded serial interfaces commonly found in high-end mobile handsets. The M2I uses fifty percent fewer processor I/O pins, freeing those pins to support desired differentiating functionality. Moreover, the M2I also deploys eight dynamically programmable I/Os that the processor can use to control and/or monitor other devices, enabling the handset designer to add even more differentiating functionality.

The M2I architecture achieves its high-performance and low-battery drain using a synchronous clocking scheme that enables the use of an internal counter that eliminates the necessity for multiple addressing. Consequently, the M2I processes 64 Kbits of data in only 4,001 cycles, compared to the 8,000 cycles required by previous-generation devices. Not only can the same amount of data be transferred in half the cycles, but also the cycles run three times faster, thus providing an overall performance increase of 6X. All this is accomplished with ninety percent less battery drain.