New design tools from Analog Devices

As the industry’s only supplier of all major RF-to-digital functional building blocks that extend from antenna to processor, Analog Devices supports its broad RF-IC portfolio with a comprehensive suite of design tools. RF systems design is an extremely complex and time-consuming process, and the company’s design tools reduce design risk by making the overall RF-to-digital design practice simpler, faster, more accurate, and more robust.

The newest addition to ADI’s portfolio of design tools, ADIsimRF furthers the company’s commitment to provide RF-system designers with innovative tools that improve performance and help ease development for both wireline and wireless communications equipment. The ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain, including cascaded gain, noise figure, IP3, P1dB, and total power consumption. The calculator can be easily switched between transmit mode and receive mode where calculations and data entry are input referred. Designers can vary the number of stages up to a maximum of 15, and additional stages can be inserted at any point in the signal chain. In addition, designers can temporarily disable individual stages, clear their data, or remove them completely. ADIsimRF also contains embedded data from many of ADI’s RF ICs. A designer can easily access this data using pull-down menus, thereby eliminating tedious data entry. The tool also includes device tables to assist in component selection.

Fully compatible with prior releases, the new ADIsimPLL Version 3.1 design tool eliminates time-consuming iterations from the PLL/synthesizer development process, thus ensuring that products reach the market faster. ADI has optimized its ADF4xxx synthesizers for applications such as wireless base stations, LAN, mobile handsets and PDAs, broadband wireless access, industrial, instrumentation and test equipment, satellite, sonar, and CATV. Analog Devices’ ADIsimPLL Version 3.1 design tool offers support for the company’s latest PLL synthesizers, including the highly-integrated ADF4350, ADF9010, ADF4360-9, and the ADF4157. In addition, the design tool includes a new simulation capability for fractional-N spurious estimation. This feature provides an initial assessment of the amplitude and offset of fractional-N spurs. It also allows the user to adjust parameters that set the spur amplitude in response to various loop filter selections, enabling RF designers to incorporate their measurements to further refine the effects of spurs within their system. ADIsimPLL version 3.1 offers an enhanced library of components, including new VCO libraries and improvements to existing component libraries. It also features new loop filter topologies and improvements to the chip-selection algorithm and the power-up simulation.