World’s first JESD204B clock buffer for 2G, 3G and 4G LTE

Promoting optimal system performance and cost efficiency, this innovative device continues the expansion of IDT’s industry-leading wireless infrastructure timing portfolio.

The IDT 8V79S690i is a two-channel JESD204B clock and SYSREF fanout buffer with configurable phase delay and extremely low additive phase noise, offering maximum design flexibility and performance. Supporting frequencies such as 614.4 MHz and 1228.8 MHz, IDT’s clock buffer addresses the latest generation of high-speed JESD204B analog-to-digital and digital-to-analog data converters, delivering high-quality, synchronous clock and SYSREF signals to improve overall base station signal quality and increase data throughput via lower system bit error rates. Furthermore, base-station developers may reduce system costs by simplifying filters as a result of less noise in the signal path. Together, the 8V79S690i clock buffer, 8V19N486i RF-PLL, and 8V19N476i clock synthesizer chipset comprise the industry’s highest-performance and most complete JESD204B clocking solution on the market.

Christian Kermarrec, vice president and general manager of the Timing and Synchronization Division at IDT, comments: “The new fanout buffer complements our RF-PLL and clock synthesizer, giving our customers the tools needed to build the highest-performance JESD204B-based systems. With additive phase jitter below 20 fs RMS at 1228.8 MHz, multiple clock fanout channels, and configurable phase delay for each SYSREF output, the 8V79S690i offers the performance and flexibility expected of IDT – the world’s leader in timing solutions. The new clock buffers increase IDT’s serviceable timing market, adding to our rich portfolio of products for wireless infrastructure applications, including performance-leading JESD204B-based data converters, data compression, RF signal chain, and RapidIO.”

Using silicon-germanium technology, the 8V79S690i clock buffer supports the distribution of high frequency clocks and SYSREF signals with low additive phase noise and high power supply noise rejection. The two-channel device offers a 1:10 LVPECL/LVDS clock fan-out, and a 1:8 LVDS fan-out for the SYSREF signal. The clock outputs are configurable for both amplitude and phase delay (101 picosecond steps) for flexibility in achieving radio board synchronization as well as fine-tuning the system for optimal performance. In addition, a configurable power-down control enables sophisticated power saving schemes for improved system efficiency.

The features offered by the 8V79S690i not only provide exceptional performance and flexibility in the radio board design, but allow system designers to save components previously required for signal level conversion and correction.

The IDT 8V79S690i is currently sampling to qualified customers and is available in a 72-lead 10x10 mm VFQFPN package.