Single-Chip System expands Semtech's ToPSync Network Timing Platform

The ACS9522T integrates a CPU, memory and six phase-lock loops (PLLs) needed to support IEEE 1588 packet-based synchronization as well as frequency synchronization via synchronous Ethernet or SONET/SDH. This closely coupled architecture delivers the industry’s best time alignment performance by offering advanced features such as synchronous Ethernet / IEEE 1588 hybrid mode operation and network asymmetry correction.



It also supports different system synchronization architectures without loss of flexibility. The revolutionary new multi-PLL architecture allows seamless integration of multiple local and network timing sources for enhanced system availability.



The device features a brand new GUI for rapid system configuration and prototyping, enabling an almost push-button process to convert the configuration into production system software. This is designed to significantly reduce costly reconfiguration and testing cycles and speed up time to market.



“The sync landscape is evolving rapidly, particularly in the wireless backhaul space” said David Spencer, ToPSync Marketing Manager. “We are now seeing synchronization required everywhere, driven by the rollout of 4G LTE small-cells, along with end applications pushing the synchronization accuracy requirements to previously unachievable levels.



“The new generation of ToPSync system software is designed to support these emerging requirements, particularly the collaborative use of IEEE1588 with more-traditional GPS, which enables a more robust and fault-tolerant 4G LTE backhaul network. And the ACS9522T provides this on the most highly integrated platform available, reducing the sync function to a single device. By using the ToPSync solution, our customers free themselves from worrying about the sync system design details and can instead concentrate on their areas of expertise, reducing time and cost to market,” Spencer said.



Key Features of the ACS9522T ToPSync Solution:



•Complete single-chip sync solution – packet and physical layer timing



•Full support for IEEE1588-2008 master, slave and boundary clock operation



•Industry-leading IEEE1588 performance through the use of Semtech’s patented clock recovery techniques – better than 300 ns phase alignment with ITU-T G.8261 10-switch test network



•Synchronous Ethernet / IEEE1588 hybrid mode to improve performance to sub-100 ns



•Dual physical-layer PLLs and dual packet-timing PLLs to support multiple clock sources



•Dual Packet Timing PLLs for multiple PTP flows



•Dual internal timebases with very flexible frequency and phase build-out features



•Fully compliant with ITU-T G.8265 “telecom profile”