Wireless
IDT Expands Industry-leading Timing Portfolio with Low-noise Timing Chipset for Wireless Base Station Radio Cards
Integrated Device Technology announced a low-noise timing chipset optimized for use in wireless base transceiver station radio cards. The new chipset complements IDT’s extensive communication signal chain portfolio, offering engineers the tools needed to solve phase noise-related challenges and build cutting-edge wireless systems.
The “At IDT, we recognize the undesired effects noise can cause in the RF signal chain, and have developed this timing chipset to provide system engineers a new tool to address it,” said Christian Kermarrec, vice president and general manager of the Timing and Synchronization Division at IDT. “Our new chipset also offers several key features, such as JESD-compliant clocking and integrated clock jitter attenuation for easy integration into our customers' specific architectures. The new timing devices complement our industry-leading timing portfolio as well as our performance-leading data converters, data compression, RapidIO®, and RF signal chain products for wireless infrastructure applications.”
The IDT 8V19N4xx chipset generates synchronized and highly configurable clock and SYSREF signals as required by JESD204B applications. This allows customers to use a standard, cost-effective timing chipset with a high degree of flexibility instead of multiple PLLs, synthesizers, and buffers. In addition, the devices feature integrated clock jitter attenuation to simplify system design, and support a low-cost, low-frequency external VCXO to reduce system cost.
Product Availability
The IDT 8V19N4xx devices are currently sampling to qualified customers and are available in standard VFQFPN packages. The RF PLL and high-frequency synthesizer can be paired with other devices for added flexibility in the application.