No unpleasant surprises in ASIC development

The answer is behavioural modelling, as explained by Dr Michael Chesterman, Senior Design Engineer at mixed signal ASIC supplier Swindon Silicon Systems.

An ASIC allows a developer to make the leap from a proof-of-concept circuit board, populated with numerous off-the-shelf components, to a volume-optimised product. By integrating all the key circuits into a single package, form factor is improved, electrical performance is optimised, and novel circuit intellectual property (IP) is hidden. At the same time robustness is enhanced, assembly is simplified, and component sourcing is streamlined.

However, ASIC design is unlike many other fields of engineering, as nothing can be physically tested until the entire fabrication process is completed, some weeks after the design work is over. It is not possible to ‘trial’ an approach or to patch a misbehaving design once it is fabricated. Instead, the designers rely on upfront simulation to predict the behaviour of the finished article and ensure that it meets the customer’s specification. The ‘SPICE’ circuit simulation tools at their disposal are incredibly sophisticated, and able to model the finest details of the design, down to the behaviour of individual transistors and the tiny fringing capacitances that form between them. But this sophistication comes at huge computational cost, and a tiny fraction of the design can take hours or days to simulate in such detail.

Taking a top-down approach

A top-down approach to ASIC design is favoured, starting from the high-level requirements that have been agreed with the customer. Determining these requirements is somewhat of an art, and Swindon are glad to provide their consultancy here: understanding a customer’s wider system and recognising the most effective role for a bespoke chip. Once the requirements are established, the project’s lead designer will develop a chip architecture comprising various analogue and digital sub-blocks, each with their own precise specification.

At this point the essence of the design has been captured. It is now highly desirable to simulate the chip, to confirm the sub-blocks will work together, to allow the performance of each block to be traded-off, and to check that the overall design will function as intended. However, SPICE simulation is still a long way off, awaiting a team of designers to implement the blocks at the transistor level. And even with transistor-level designs in hand, it is unfeasible to simulate an entire chip using conventional SPICE: a small mixed-signal ASIC may still contain tens of thousands of transistors, and so the computational demand is impractical.

This prompts a need for a model with a higher degree of abstraction, which can be constructed rapidly from the sub-block specifications, and can run quickly at chip-level to confirm functionality. This need is fulfilled with behavioural models.

Behavioural models

A top-level behavioural model of an ASIC is composed from individual ‘black-box’ models of each sub-block, connected exactly as the chip architecture demands. In this context, ‘black-box’ signifies that no assumption is made about the inner working of the blocks: it is only behaviour at their terminals that is approximated. But what degree of approximation should be used? For this, it is important to remember that the main purpose of the models is to verify correct interaction between the blocks. Therefore, designers must write the simplest, coarsest models that are able to achieve this.

Once in place, the sub-block behavioural models serve as a valuable verification tool. While the analogue blocks are being implemented, designers can use the models as a reference, comparing simulation of the model against that of the emerging transistor-level design. The top-level model allows the digital portion of a mixed-signal ASIC to be systematically and rigorously tested, by predicting its interactions with surrounding analogue circuitry.

This is particularly important where digital and analogue circuits work together closely, for example when a CPU is controlling various analogue blocks: perhaps orchestrating analogue measurements by enabling & configuring circuits at the correct times. These scenarios merit particular care in verification, as there can be many pitfalls in the sequencing of events. For example, an amplifier might be enabled before the reconfiguration of a power-supply, leading to an unanticipated supply brown-out. Behavioural models of analogue sub-blocks are uniquely positioned to catch these faults, as they can be devised to ‘complain’ – by raising a warning or error message – when subjected to a stimulus that is out-of-range or otherwise invalid.

Empowering the customer

Besides its role in verifying the ASIC design, behavioural modelling can serve as a collaboration tool. The top-level model can often be shared with the customer, allowing them to interact with their proposed chip using a testbench that represents their application. All this can happen before block-level implementation has begun, validating the customer’s requirements, and building early familiarity with the product they have commissioned. Furthermore, for designs that incorporate a CPU, the top-level behavioural model can even host the embedded software. This allows the software to be prototyped and its interface with the bespoke hardware to be trialled before any analogue sub-block design has taken place.

Nobody wants an unpleasant surprise, in any area of manufacturing. Behavioural modelling is a powerful verification tool in a top-down ASIC design process, and its use is synonymous with first-time success. It provides the customer with deep insight into their investment, and builds confidence in its specification, all at the very earliest stages of design. Ultimately, behavioural modelling ensures the customer gets the ASIC they need.