Test solution readied for LPDDR4 2015 adoption

22nd September 2014

Tektronix

Mick Elliott

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JEDEC LPDDR4 is slated for adoption in 2015, not too far off. It builds on the current generation of LPDDR3 technology and will deliver improved data rates up to 4.26 Gb/sec and use an ultra-low voltage core to reduce power consumption by approximately 35 percent to enhance performance in mobile devices like smartphones, wearables & tablets.

So with excellent timing Tektronix has introduced what it claims is the industry’s first complete PHY layer and conformance test solution for JEDEC LPDDR4.

It will introduce new test and measurement challenges due to lower input/output voltage of just 1.1V, higher data rates and compact mechanical designs that limit access to test points. There are also multiple changes in Vref, read burst and write burst which further increase the complexity to perform the tests mandated by the JESD209-4 specification.

Through automated set-up and test execution, the Tektronix solution can reduce testing cycles from a week or more to a single hour.

With this introduction, Tektronix now offers integrated PHY layer testing and debug of the new LPDDR4 standard in DDR-LP4 analysis software. By automating test setup and execution, DDR-LP4 gives memory designers the confidence that they are in full conformance with memory standards. Should a memory system fail conformance tests, designers can quickly switch to debug mode and use tools like the powerful Visual Trigger capability on Tektronix oscilloscopes to isolate events of interest for deeper root-cause analysis with the DPOJET Jitter and Eye measurement toolkit.

In conjunction with partner Nexus Technology, Tektronix is also introducing the industry's first LPDDR4 memory component interposers featuring two patented interposer designs.

EdgeProbe interposers are designed for the demanding mechanical constraints required by mobile designs while socketed interposers are available for ease of use, reusability and component swapping.