Programmable clock generators meet rigorous jitter requirements

These are the sixth generation of IDT VersaClock programmable clock technology, with enhancements for high-performance electronic systems. With RMS phase jitter less than 500 fsec over the full 12 kHz-to-20 MHz integration range, the devices meet the jitter and phase noise requirements of applications such as 10G Ethernet, enterprise storage SAS and SATA, PCI Express Gen 1/2/3, PHY reference clocks and the newest generations of high-end FPGAs — all while operating at about half the core power of competing devices.

The devices’ core current consumption of 30 mA eases system thermal constraints and reduces operating power expenses. In addition, the VersaClock 6 devices are footprint compatible with their VersaClock 5 counterparts, enabling performance scalability with minimal design changes.      

Output frequencies are generated from a single reference clock, which can come from one of two redundant clock input pins.

Either of the clock input pins can be selected during operations. A glitchless manual switchover feature allows one of the redundant clocks to be selected during normal operation without interfering with the generated output clocks.      

The VersaClock 6 devices are programmable through an I2C interface. One of two selectable I2C bus addresses can be used, allowing two VersaClock 6 generators to be used in the same system without address conflicts. The internal configuration of the device can be easily set in the internal One‑Time Programmable (OTP) memory, or it can be modified using the I2C interface.      

Applications for the VersaClock 6 include high-performance consumer devices, networking systems, industrial applications, computing systems, and data-communications applications.