Frequency Control
Clock synthesisers feature very low phase-noise performance
IDT has announced the availability of the latest member of its FemtoClocks family – the FemtoClock Next Generation (NG). This new family of clock synthesisers features very low phase-noise performance and significantly improved power-supply noise rejection, allowing for increased bandwidth when used with serial interfaces.
The As with previous generation FemtoClocks, the new IDT timing solutions are designed to work in conjunction with other devices on the board that require a reference clock, such as PHYs, switches, ASICs and network processors. The result of this cohesive nature between devices is a simplified board design and layout, as well as improved time-to-market. Moreover, the family meets the specification requirements of all interface standards, such as 10Gbit Ethernet, PCI Express, Fibre Channel and SONET.
The first device in this family, the 843N156-125, generates a 125MHz single-ended output and a 156.25MHz LVPECL output from a single 25MHz crystal, replacing two crystal oscillators on the board with one device, providing application architects with increased design flexibility. The typical root-mean-square (RMS) phase noise jitter for both frequencies is 400fS, making these perfect for PCIe, Gigabit Ethernet and 10Gbit Ethernet applications, since it gives designers ample margin in their designs to meet the jitter requirements of these standards. Additional FemtoClock NG members will feature output frequencies of up to 1.3GHz, providing integrated silicon solutions with short lead times when compared to crystal and SAW oscillators. Samples are available now for qualified customers, in 16lead TSSOP packages.