SoC design suite boosts FPGA designer productivity

The Libero SoC version 12.0 aims to deliver new gains in runtime and quality of results, as well as one unified design suite for all the company’s latest-generation FPGA families, including new production releases of PolarFire FPGAs.

Libero SoC v12.0 reduces design flow runtimes and, with the improved quality of results, it provides results in fewer design iterations and improves customer productivity. By upgrading to Libero SoC v12.0, designers will reportedly see runtime reduction of 60% for timing, 25% for place and route and 18% for power results. They will also see an average increase of four percent in quality of results for larger designs and a ten percent improvement for the PolarFire MPF300/TS-1 device.

“Libero SoC v12.0 is the result of our determination to offer a comprehensive, easy-to-adopt, easy-to-learn FPGA design suite,” said Rajeev Jayaraman, Vice President of Software for the FPGA Business Unit at Microchip’s Microsemi subsidiary. “This latest release is focused on delivering the many essential elements needed for efficient design implementation, while further enabling the growing adoption of the low-power PolarFire family across each of our key market segments.”

Libero SoC v12.0 is being released simultaneously with the production release of the PolarFire MPF100T, PolarFire MPF200T and PolarFire MPF300T devices. The release includes production timing and power for PolarFire MPF300T-1 devices, as well as support for two new devices for the aerospace and defence market segments; the low-power, radiation-tolerant RT4G150L, which claims to offer 25% savings for standard speed grade; and military-grade support for the SmartFusion2 M2S150T/S FCV484 device.

One unified design suite for PolarFire, IGLOO2, SmartFusion2 and RTG4 FPGAs eliminates the need for designers to qualify multiple pieces of software when working across product families. Libero SoC v12.0 now supports FPGA Hardware Breakpoint (FHB) for RTG4 and PolarFire devices, PCIe debug support for PolarFire and continuous transceiver eye monitoring using SmartDebug.

The new release also improves Double Date Rate (DDR) memory performance by an average of 29% in high-effort mode and 39% in regular-effort mode. Enhanced Tool Command Language (TCL) support enables a much-requested feature where customers can run the entire design flow on the command line if they so choose.

Microchip’s Libero SoC v12.0 design suite is available now to support customers designing with its PolarFire, IGLOO2, SmartFusion2 and RTG4 FPGAs.