Redefining the midrange?

It’s no secret that Altera and Xilinx compete, ostensibly, for the same design sockets within ‘power’ applications (predominantly in the telecommunications market) and that the rest of the FPGA vendors are ‘ok with that’; after all, it requires a lot of money, effort and risk to develop on the bleeding edge, which is invariably where the top-end FPGAs have to be in order to win those design sockets.

While there are a limited number of design slots for high-end FPGAs, the ‘everything else’ market for FPGAs is vast and reportedly increasing. According to Microsemi’s Vice President of Marketing, Paul Ekas, the market for FPGAs with up to 150,000 logic elements (LEs) is worth in excess of $1 billion (excluding the consumer market). Even with their higher selling price, this means the ‘performance’ end of the market may not be the most lucrative.

On paper, it makes sense to target a market that carries lower risk and has less demanding performance requirements with higher volumes, even if it does carry a lower average selling price. It’s something most FPGA vendors seem to have acknowledged and are developing new devices targeting this part of the market. That means competition in the midrange isn’t restricted to a subset of FPGA vendors, and as technology advances trickle down the product tree it also means that midrange devices are increasingly capable of taking on more demanding applications.

Midrange Spread

The term midrange is probably easier to define in terms of applications, because from an FPGA vendor’s point of view a midrange device is a relative term; each new generation of FPGA pushes performance up. Unlike the ‘power’ end of the market — customers who will make use of the fastest, widest and largest FPGA — the market for midrange devices is a little more discerning and so the devices need to be ‘tuned’ accordingly.

Both Altera and Microsemi have just announced new technology platforms and, subsequently, new midrange devices. Arguably, they have both chosen the option of delivering more than ‘just enough’ performance, but not too much.


Microsemi’s Igloo 2 family is being marketed as a 'cost-optimised' solution, with up to 150k LUTs

Microsemi’s Igloo 2 family spans 6,000 to 150k logic elements and is designed on an all-new 4LUT (look-up table) fabric; the existing Igloo family uses a 3LUT fabric. According to Ekas, the choice to limit the family to 150k LEs was commercial but the fabric is optimised for this density, which means if Microsemi chooses to increase density it will probably need to redesign the fabric.

The move from 3LUT to 4LUT has pushed up the baseline performance of the fabric; it is reportedly five times faster than the Igloo range. Measuring FPGA performance is largely application-dependent, but Ekas stated that Igloo 2’s performance is on a par with midrange devices offered by other FPGA vendors.

Going in hard

In its 30th year since incorporation, Altera has just released the first details of its 10th generation of FPGA, which it has chosen to call Generation 10. This sees both the Arria and Stratix families getting a technology upgrade and perhaps of most interest is the news that the flagship family, the Stratix, will be manufactured using Intel’s 14nm Tri-Gate process (known elsewhere in the industry as finFET). This will enable developers to choose — in terms of performance or power efficiency, depending on the application’s needs — how to best make use of that new technology.


Altera is, for the moment, not disclosing what core the 3rd Generation processor system will be based on

For example, in comparison to the Stratix V, if maximum performance is needed the Stratix 10 can deliver a 2-fold improvement for ‘only’ 30% more power. Conversely, if the performance offered by the Stratix V is adequate, engineers can reduce power by as much as 70%. This power/performance tuning comes in both the FPGA and SoC versions of Stratix 10, with the SoC variant also featuring a new ARM Cortex processor sub-system. Currently the Stratix V SoC uses the ‘first generation’ of processor sub-system, based on a dual-core Cortex-A9 configuration. The configuration for the Stratic 10 hasn’t been announced but Altera is differentiating it from the sub-system its integrating in to the Arria 10 SoC (which it has dubbed ‘2nd Generation’) by referring to it as ‘ultra high-performance’ 3rd Generation. This could suggest the core being used in the Stratix 10 SoC isn’t the A9 but something more advanced, such as the A12; heralded as the A9 successor thanks to delivering higher performance at the same power.

What is known already is that the 2nd Generation processor sub-system, as being integrated in to the Arria 10 SoC, will run at 1.5GHz (which is almost twice as fast as the 1st Generation sub-system), and is (still) the Cortex-A9 MPCore.

Altera admits to being ‘surprised’ by the level of interest and uptake of the ARM-based SoC members of its FPGA families, stating that demand could overtake demand for non-SoC devices.

Low end

If the midrange is difficult to quantify then the definition of a low-end application must be equally vague, particularly given that the cost of entry-level FPGAs is tumbling. The latest indication of this came from Lattice Semiconductor recently, when it introduced what it claims to be the industry’s smallest FPGA; the iCE40 LP384 (which offers 384 LUTs). The roadmap for the family includes a 2mm2 package at a price of $0.50 in multi-million volumes.


Lattice is targeting sensor hub applications with its tiny iCE40 family

One of the target applications for this tiny FPGA is sensor hubs in devices that fall under the heading of ‘the Internet of Things’. This is still an emerging mega-trend, of course, but the industry expects to see the number of connected devices rise in to the multiple billions within the next decade (the actual figures vary depending on the source of the research). The majority of these devices will be sensor-based, relaying data through the internet. Given the lack of standardisation in sensor interfaces, a small FPGA may be the way to go.

FPGAs consistently extend their usefulness, either by integrating more hardwired functionality or extending the performance of the underlying fabric. Following the standard cost model, they also continue to fall in price, promoting their position as the alternative to ASIC and, increasingly, ASSPs.