Altera and Micron Lead Industry with FPGA and Hybrid Memory Cube Interoperability

the limitations imposed by conventional memory technology, and provides ultra-high system performance with significantly lower power-per-bit. HMC delivers up to 15 times the bandwidth of a DDR3 module and uses 70 percent less energy and 90 percent less space than existing technologies. HMC’s abstracted memory allows designers to devote more time leveraging HMC’s revolutionary features and performance and less time navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation. Micron expects to begin sampling HMC later this year with volume production ramping in 2014.

“As one of the founding developers of the HMC Consortium, Altera’s support for and involvement with HMC has been invaluable,” said Brian Shirley, vice president of DRAM solutions for Micron Technology. “The combination of Altera FPGAs with Micron’s HMC solution will help customers leverage the technology’s performance and efficiency in a wide range of next generation networking and computing applications.”

Altera’s 28 nm Stratix V FPGAs are an ideal demonstration of HMC technology since they are the highest performance FPGAs in the industry with a two speed-grade advantage over the nearest competitor. This performance enables the FPGA to leverage the full bandwidth, efficiency and power benefits of HMC by using a full 16 transceiver HMC link.

“By demonstrating Stratix V and HMC working together now, we are enabling our customers to leverage their current development with Stratix V FPGAs and prepare for production deployment in Altera’s Generation 10 devices, knowing they will have proven HMC support,” said Danny Biran, senior vice president of marketing and corporate strategy at Altera. “The partnership between Altera and Micron to deliver this capability puts our customers at the forefront of innovation.”

Altera’s Generation 10 Devices Deliver Performance

Arria 10 FPGAs and SoCs are the first device families in the Generation 10 portfolio and will be the first devices to support HMC technology in volume production. Leveraging an enhanced architecture optimized for TSMC’s 20 nm process, Arria 10 FPGAs and SoCs will use HMC to extend the benefits by providing both 15 percent higher core performance than today’s highest performance Stratix V FPGAs and up to 40 percent lower power compared to the lowest power Arria V midrange FPGAs. Arria 10 FPGAs and SoCs will offer up to 96 transceiver channels, enabling customers to take full advantage of the bandwidth that HMC has to offer.

Stratix 10 FPGAs and SoCs will enable the most advanced, highest performance applications across communications, military, broadcast and compute and storage markets. These high-performance applications often require the highest memory bandwidth, which drives the need for an HMC-ready architecture. Leveraging Intel’s 14 nm Tri-Gate process and an enhanced high-performance architecture that integrates with HMC technology, Stratix 10 FPGAs and SoCs will enable system solutions with an operating frequency over one gigahertz, and two times the core performance of current high-end 28 nm FPGAs. Stratix 10 devices will also allow customers to achieve up to a 70 percent reduction in power consumption at performance levels equivalent to the previous generation.

Availability

Altera Stratix V FPGAs are available now in volume production. The Stratix V and HMC demonstration is accessible for evaluation and will be in production with Arria 10 devices. First samples of Arria 10 devices will be available in early 2014, with Quartus II design software support available now in early access. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and design software support in 2014.