Latest patent on zero-leakage high-voltage analog switches

It is particularly of interest for low-ohmic (low RDSon) switch matrix architectures for the medical, automotive, industrial and consumer markets. High current switch matrix topologies require the use of low-ohmic (D)MOS switches.

The desire to have fast switching times (small time constant, small R1) and low leakage (large R1) can not be accomplished with a traditional architecture due to the conflicting requirement on R1. “We have designed a novel circuit to eliminate this conflicting requirement and are able to reach fast switching while having virtually zero-leakage.

Moreover, in this classical floating pass-switch design the connected lines are loaded when the switch is enabled/disabled. This results in unwanted and inaccurate readings in applications such as high-impedant, high-voltage multiplexers and high-accuracy, high-voltage readouts like piezo-electrical transceivers” says Tim Piessens, CTO of ICsense.

“We will use this patent to offer ASICs to our customers with increased accuracy and at the same time fast switching and zero-leakage. Our newest patent applies to single MOS switches and to back-to-back topologies that allow full-range isolation,” says Tim.

The design is particularly interesting for applications with low RDSon requirements (<5Ohm) and heavy constraints on point loading. Additionally, high-voltage switch architectures benefit from the patent because it can cope with negative voltages and polarity changes.

In the past, ICsense has patented other inventions. To produce more cost effective wafers, the company patented a circuit which regulates stacked transistors to provide higher voltage swing (both drive and sense) in plain CMOS processes.

The principle uses control techniques to guard the SOA. With this invention it is possible to elevate the operational voltage of a plain low-cost CMOS process by a factor of x4. Since 2010, this patent is exploited in ICs which are in mass production by companies such as NVidia.