The GW5AT-15, the latest addition to the Arora-V FPGA family, features multiple hard-core SerDes transceivers, high-speed memory, and 15,120 logic elements. It is available in several package options, including a compact 4.9mm x 5.3mm WLCSP, which provides a maximum SerDes throughput of 12.5Gbps.
Arora-V products and the GOWIN EDA development environment will be showcased at GOWIN’s booth 708 at the Sensors Converge Expo (Santa Clara, California, 25-26 June 2024).
The GW5AT-15's features are ideal for emerging applications that demand very high bandwidth for video and other data-transfer purposes while requiring a small board footprint. These applications include consumer tablets, augmented/virtual reality headsets, and car infotainment systems.
The high SerDes bandwidth of the GW5AT-15 makes it perfect for high-speed interfaces. Key features include:
- 3-lane MIPI C-PHY operating at up to 5.75Gbps per lane
- 4-lane PCIe 3.0
- 4-lane MIPI D-PHY operating at up to 2.5Gbps per lane
The GW5AT-15 also supports high-speed USB Type-C and other USB connections through its on-chip USB 3.x and USB 2.x PHYs.
GOWIN’s CEO Jason Zhu said: "The market for high-speed display and camera interfaces has been stuck with a choice of high-end FPGAs which are large, expensive and power-hungry, or low-end FPGAs with inadequate SerDes performance. Our latest Arora-V device perfectly fills the gap, offering a unique hard-core MIPI C-PHY and D-PHY capability in a small and highly affordable FPGA."
New applications include 4K gaming tablets, where the GW5AT-15’s high throughput meets the demands of high frame-rate 4K video. In vehicle infotainment systems, its high-speed USB and other interfaces enable cars to emulate the smartphone user experience more effectively through applications like Android Auto™ or Apple CarPlay.
All SerDes operations are supported by co-packaged fast memory resources, including:
- 118kb of shadow SRAM
- 630kb of block SRAM (BSRAM) arranged as 35 x 18kb
- Optional 64Mb (in MG132P package) or 128Mb (in CM90P package) of pseudo SRAM (pSRAM)
- Optional 8Mb of NOR Flash
The FPGA also features two on-chip PLLs, multiple clock sources, a JPEG codec, and an ADC.
Like other members of the Arora-V family, the GW5AT-15 is built on a low-power 22nm TSMC process. It is supported by the GOWIN EDA FPGA design environment, which includes an FPGA design tool, IP cores, and reference designs. The design tool supports SystemVerilog, Verilog, and VHDL programming languages.
