Xilinx Picks 28nm High-Performance, Low-Power Process to Accelerate Platforms for Driving the Programmable Imperative

Today, numerous trends - the exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing - are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.

At the same time, power management and the impact it has on system costs and performance is a paramount concern to today's electrical system designers and manufacturers. The need to reduce power consumption and manage thermal dissipation, while also keeping ahead on price and performance-driven capabilities, is essential as competitive pressure increases.

At the 28nm node, static power is a very significant portion of the total power dissipation of a device and in some cases is the dominate factor. To achieve maximal power efficiency, the choice of process technology is paramount because the key to enabling greater useable system performance and capabilities is controlling power consumption, said Victor Peng, senior vice president, Programmable Platforms Development at Xilinx. We chose the high-k metal gate high-performance, low-power process at TSMC and Samsung Foundry for next-generation FPGAs to significantly minimize static power consumption so we wouldn't lose the performance and functional advantages we get at 28nm. At 28nm, we are continuing our strategy of exploring and working with more than one foundry partner at each node in the interest of technical risk mitigation and cost/capacity leverage.

Compared to the standard high-performance process, the high-performance, low-power process delivers FPGAs that are 50% lower in static power. The lower static power enables Xilinx to provide customers with the lowest-power FPGAs in their class, and contributes to a 50% reduction in total power compared to previous generation devices. Meanwhile, next-generation development tools reduce dynamic power as much as 20% through innovative clock management. Enhancements made to Xilinx's industry-leading partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33%.

To address system performance bottlenecks caused at the interconnect level, Xilinx will provide the industry's highest performance interfaces to support customers who need high-bandwidth chip-to-chip, board-to-board, and box-to-box connections. This is of critical importance as customers increasingly look to FPGAs to become a major, if not central, component of their systems, and helps define how the next generation of FPGAs will enable customers to build their systems when ASIC and ASSP options are unavailable.