Xilinx ISE Design Suite 13.2 Steps Up Designer Productivity and Brings Partial Reconfiguration to Kintex-7, Virtex-7 FPGAs

In addition, this latest edition of ISE Design Suite provides an up to 25 percent performance increase in designs targeting Virtex-7 2000T devices, the industry's largest density FPGAs built using Stacked Silicon Interconnect technology. The latest ISE software release also has enhancements to the PlanAhead(TM) design and analysis tool, providing partial reconfiguration support for Virtex-7 and Kintex(TM)-7 FPGAs, and front-to-back, integrated project management environment for improved productivity in designs targeting Spartan®-6 FPGAs, Virtex-6 FPGAs, their defense grade counterparts, and all three 7 Series families including initial support for the low-cost Artix(TM)-7 family.

Improved Productivity from PlanAhead tool

The award-winning ISE Design Suite provides designers the tools they need to facilitate global-team design, rapid feedback on key design considerations, best practices for low-power optimization using the XPower Estimator tool, and dynamic power reduction through intelligent clock-gating - all of which is accessible via the PlanAhead tool.

The PlanAhead tool has evolved from a world class I/O pin planner and floorplanner to a comprehensive development environment that accelerates time to production with unique integrated front-to-back environment that includes design analysis at each phase of the design cycle - RTL development, IP integration, verification, synthesis, place and route. The end result is rapid convergence on power consumption, resource utilization, and performance with fewer time-consuming design iterations.

A key productivity advantage of PlanAhead is the tight integration of the design creation, analysis, planning and implementation features. With traditional FPGA flows, feedback on critical design parameters is only available late in the design flow, said Tom Feist, Senior Director of Software and Tools Marketing at Xilinx. While runtime for synthesis and place and route continues to be a top focus for Xilinx, reducing the number of design iterations is just as important for accelerating development. Up front design analysis and design preservation flows that ensure timing from run to run are critical for our customers targeting our new 7 Series devices.

Enhancements to the PlanAhead tool include new clock domain interaction reports, tooltip language localization, and Simultaneous Switching Output (SSO) support for 7 Series flip chip BGA (FFG) packages. Updates to XPower Estimator (XPE) tool enables designers to make power-consumption predictions with a high-level of accuracy and see how Xilinx's choice of TSMC's high-k metal gate (HKMG) high performance low power process, and a unified FPGA architecture across families, deliver the lowest power of any FPGA in their class in most typical designs. To learn more about Xilinx's lower power advantage, please visit: www.xilinx.com/power.

Plug-and-Play IP Initiative Continues to Move Forward

In further support of Xilinx's Plug-and-Play IP initiative, ISE Design Suite 13.2 enables Advance eXtensible Interface (AXI) interconnect support in CORE Generator(TM) system to build higher performance point-to-point architectures. Design teams building their own AXI compliant IP can now run simulations of the AXI interconnect protocol using the optional AXI BFM (bus functional model) verification IP to easily ensure all interface transactions are working properly (See User Guide: AXI Bus Functional Model v1.1 ). The AXI BFM is now available for ISim as well as Cadence, Mentor and Synopsys simulators. Users can now also access AXI_PCIe cores from the Embedded Development Kit in designs targeting Virtex-6 and Spartan-6 FPGAs. Additionally, the ChipScope(TM) AXIMonitor core in the Embedded Development Kit now supports monitoring of the AXI3 interface and includes an optional AXI Protocol Checker. The AXI Protocol Checker is designed around the ARM SystemVerilog assertions and supports 39 Ready/Valid handshake checks. For more about Xilinx's adoption of AXI, please see the White Paper: AXI4 Interconnect Paves the Way to Plug-and-Play IP.

4th Generation Partial Reconfiguration

Partial Reconfiguration support for Kintex-7 and Virtex-7 families is now also available in PlanAhead. Partial Reconfiguration dynamically modifies logic blocks while the remaining logic operates without interruption. This means designers can use either Virtex-7 or Kintex-7 devices to build flexible systems that are able to swap functions and perform remote updates while operational. Partial reconfiguration also allows designers to reduce costs and design size by taking advantage of time-multiplexing that ultimately leads to reduced board space and minimizes bitstream storage because smaller, or fewer, devices can be utilized. Smaller and fewer devices can also lead to reductions in system power, while swapping out-power hungry tasks can minimize the FPGA's dynamic power consumption. When Artix-7 family support is rolled in with the release of ISE Design Suite later this year, it will be the first time that Xilinx has offered partial reconfiguration for the entire range of FPGA families in a single generation.