Flexras Technologies Enhances Wasga Compiler Partitioning Tool

Flexras will demonstrate Wasga Compiler for the Virtex-7 FPGA-based systems at DAC, Booth #1324, June 2-5, 2013, Austin,TX, USA.



“Flexras' announcement of their support of the Vivado Design Suite and the Virtex-7 FPGA platform clearly reinforces Xilinx’s leadership in this marketplace. The tremendous growth in ASIC SoC complexity is fueling the demand for ever larger FPGAs and multi-chip partitioning tools,” says Kirk Saban, Virtex-7 Product Line Manager at Xilinx.



“Collaboration with Xilinx has allowed us to optimize our partitioning flow for next generation SoC implementations based on Virtex-7 All Programmable FPGA-based prototyping systems,” said Hayder Mrabet, CEO of Flexras Technologies. “With its timing-driven automatic partitioning and high speed Virtex-7 FPGA Advanced Pin Multiplexing IP for inter-FPGA communications, Wasga Compiler enables very fast prototyping of complex SoCs, achieving efficient results in days, or even hours.”



What’s New



Enhancements to Wasga Compiler include:

● Virtex-7 FPGA Advanced Pin Multiplexing IPs using Serdes and LVDS

● Automatic generation of XDC pin-planning and timing constraints for Vivado Design Suite

● Logic replication and pruning to optimize connectivity between FPGAs

● Modeling of inter-FPGA configurable cables



The Wasga Compiler Design Suite supports Dini boards, including the DNV7F2A. It is also included in Reflex’s FPP25 offering. Semiconductor companies, using off-the-shelf or in-house custom boards that include Virtex-7 and other FPGAs, are already benefiting from Flexras’ latest development.