VIA’s Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65 Nanometers

“Compared to our previous routing solution, the Cadence Space-Based Router provided dramatic benefits in four areas: automation, throughput, density and reduced design rule checker (DRC) count,” said Beth Longwell of Centaur Technology. “For example, we cut our routing cycle time in half, and block densities were increased up to 25 percent while meeting clock route requirements.”

The Virtuoso Space-Based Router helps designers achieve shorter time to convergence, better quality of silicon, and differentiated products for consumer and wireless markets. Its high capacity easily handles flat and hierarchical data for 250,000 net designs, while its high-performance, multi-threaded implementation accelerates completion of the largest designs. The innovative hierarchical, 3-D space-based architecture enables accurate modeling, manipulation and checking of sophisticated geometries and constraints for sub-65-nanometer interconnect design closure. And its signoff-quality advanced design-rule interconnect checking system delivers correct-by-construction design closure.

“VIA’s Centaur team experienced firsthand the benefits of using the right routing technology on advanced-node designs,” said John Stabenow, technical marketing group director at Cadence. “Its state-of-the-art Nano 3000 Series processors validate the efficient and cost-effective routing made possible by the Virtuoso Space-Based Router.”