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VeriLogger Supports Symbolic Libraries and Runtime Optimizations

23rd March 2012

SynaptiCAD

ES Admin

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SynaptiCAD has recently released an updated version of their Verilog simulator, VeriLogger Extreme. The new version supports compiling source files to symbolic libraries, enabling faster compiles of designs that share a common set of source files such as ASIC/FPGA libraries.

The new version also performs gate-level and cycle-based optimizations for faster simulation times (5x faster on gate level designs, 6x faster on designs that use cycle-based coding practices). Other enhancements include reduced memory consumption during compilation and simulation, faster design elaboration, increased compatibility with 3rd party simulator language-extensions, and support for more Verilog 2005 features.

Free 6 Month license

For a limited time, SynaptiCAD will be giving away free no strings attached 6 month licenses for VeriLogger Extreme. Free licenses will be available for both Linux and Windows versions of the simulator. Unlike the lower cost simulators typically provided with FPGA tools, SynaptiCAD's simulator is being distributed without any code that slows down the simulator when run on larger designs.

Pricing

A perpetual node-locked license for the VeriLogger Command-Line simulator sells for $2000 on Windows. Floating licenses sell for $4000 on Windows and $5000 on Unix. SynaptiCAD also sells a node-locked bundled version of the simulator combined with the BugHunter graphical debugger for $4000 on Windows. Lease pricing is also available.