Verification solution adopted for automotive IC development flow

The Cadence fault simulation technology can effectively address the many complexities associated with automotive design verification. The simulator allows for successful fault effect analysis for various fault modes that are required for achieving compliance with the ISO 26262 standard, including single event transient (SET), single event upset (SEU), stuck-at 0/stuck-at 1, and dual-point faults, while outperforming existing design-for-test (DFT)-based flows for safety-related fault effect analysis. Additionally, a congruent tool chain with Cadence Incisive® logic simulators enables a reduction in design modification time and allows for the re-use of existing testbenches for fault injection simulations.

“The Cadence Functional Safety Verification Solution has enabled us to successfully verify that our ICs and LSIs for the automotive market are ISO 26262 compliant,” said Akira Nakamura, LSI Product Development Headquarters, ROHM CO. “The fault simulation has made it easy for us to handle various fault modes, including transient faults, and allowed us to reuse testbenches without any additional modifications. We’ve obtained a reliable, robust solution that we can depend on for our automotive designs.”

The Cadence Functional Safety Verification Solution automates what can otherwise be a manual, time-consuming process of complying with functional safety requirements. It is part of the Cadence Verification Suite’s application-optimised solution for automotive devices. It also supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.