TSMC Certifies Cadence Tempus Timing Signoff Solution for 20nm Designs

“Tempus timing signoff technology elevates timing analysis performance to a new standard by leveraging distributed processing and innovative incremental timing technology,” said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. “We worked closely with TSMC to ensure that Tempus results met their strict criteria that leads to working silicon and robust designs.”

TSMC accuracy certification requirements for the Tempus Timing Signoff Solution spanned base delay calculation and signal integrity with glitch bump calculation. These two areas are required in order to have a complete timing and signal integrity analysis solution.

“Certification is an integral part of TSMC’s overall design ecosystem,” said Suk Lee, TSMC senior director, design infrastructure marketing division. “Cadence Tempus timing signoff tools are ready to address the design challenges of future TSMC process nodes. We worked closely with Cadence so Tempus could pass our acceptance criteria, and we look forward to teaming with them on future technologies.”

The Cadence Tempus signoff technology offers:

-High-performance parallel processing for full flow timing analysis
-Scalable architecture to handle designs with hundreds of millions of cells
-Tempus integrated closure environment, which provides for MMMC (multi-mode, multi-corner), physically aware timing closure with multi-threaded and distributed timing analysis