Trace capabilities for RISC-V development

In addition, this new version includes enhanced implementation of the draft P extension and intrinsics with support for the vectorised versions.

Through excellent optimisation technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimise the utilisation of on-board memory. The latest version introduces several new compiler optimisations for speed and size, in addition to new optimised libraries for string handling.

This results in improved size optimisations across a wide range of standard code bases, as well as significant improvements in speed optimisations for real-world benchmarks. To ensure code quality, the toolchain includes C-STAT for integrated static code analysis. C-STAT proves code alignment with industry standards like MISRA C:2012, MISRA C++:2008 and MISRA C:2004, and also detects defects, bugs, and security vulnerabilities as defined by CERT C and the Common Weakness Enumeration (CWE).

As previously announced, a functional safety edition of IAR Embedded Workbench for RISC-V, certified by TÜV SÜD according to IEC 61508 and ISO 26262, will be available in early 2021, delivering qualified tools, simplified validation and guaranteed support through the product life cycle.

IAR Embedded Workbench offers native support for powerful debugging and trace probes, enabling additional capabilities for monitoring and understanding an application’s behaviour. The debug probe I-jet supports on-chip RAM buffered trace, in addition to fast JTAG/cJTAG/DAP debug. For livestreaming of trace information for code coverage and profiling purposes, developers are able to use the trace probe I-jet Trace.

With I-jet Trace, IAR Embedded Workbench provides developers with full control of all active settings and the live trace status of the application. In addition, function profiling makes it possible to see and analyse timing information for the functions in an application, while code coverage analysis shows the percentage of code that has been executed down to single instruction resolution.

These combined capabilities offer a non-intrusive and easy-to-use code optimisation tool. With the latest version of IAR Embedded Workbench for RISC-V, the trace capabilities are extended with enhanced support for the SiFive Insight debug solution and added support for Trace trigger points, making it possible to tailor when to start and stop trace capture.

IAR Systems is exhibiting at the virtual RISC-V Summit December 8^th to 10th, 2020, and Robert Chyla, Lead Emulation Architect at IAR Systems, will present the topic ‘Overview of Trace for RISC-V’ in the Software & Tools stream on Thursday, December 10th, 2:00pm - 3:30pm PST (Pacific Standard Time, GMT-8).

IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain. For developers who want to try the toolchain, IAR Systems provides a RISC-V evaluation kit free of charge to companies with commercially viable development projects.