Tools achieve certification for TSMC’s 16nm FinFET process

15th April 2014

Staff Reporter

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Digital tools from Cadence Design Systems have received V1.0 DRM and SPICE certification for TSMC’s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence tools. Cadence’s digital, custom/analog and signoff tools have been co-optimized with TSMC’s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.

The Cadence digital RTL-to-signoff and custom/analog tools receiving the V1.0 DRM certification are: Cadence Encounter Digital Implementation System, Physical Verification System, QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment and Spectre Simulator.

“To drive the continued adoption of advanced process technologies such as 16nm FinFET, customers must be confident that the design tools and manufacturing process have been tested to ensure they work together seamlessly,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We worked closely with Cadence to certify these design tools and incorporate them into the TSMC Reference Flows so our customers can meet their time-to-market goals and stay competitive in advanced technology design.”

“The combination of our early investment in FinFET technology development and long-term partnership with TSMC enabled Cadence to quickly achieve V1.0 DRM certification,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer at Cadence. “Several of our customers are already using these tools and flows to design in TSMC’s new process technology to deliver innovative new devices.”